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开始于 唐Y 2020年6月27日
On 2020-06-27, 唐Y <blockedofcourse@foo.invalid> wrote:
> Are there any processors/PMMUs for which the following would be true (nonzero)? > > (pagesize - 1) & pagesize
I'm a little late into this discussion but the first points that came to mind don't seem to have been addressed elsewhere in the thread. My first thought was of systems with software TLB replacement - ultimately the system developer has greater lattitude in how the pages get laid out but then I realised that can only be at the hierarchy level, i.e. so many pages of pages, so many pages of pages of pages etc. The fundamental size of a page has to be as defined by the hardware (either one or a set of options) to determine which bits get translated. That itself hints that the expression must be a contradiction, if page sizes where not 2^n then the low order bits would not remain constant in translation 和 you wouldn't be able to identify a page simply be looking at the high order bits - you'd need to introduce comparisons, additions 和 subtractions. I suppose it could be done but you'd wasting an awful lot of silicon 和 a lot of time on each access for no clear reason, so in the absence of an actual example I would discount such an architecture as purely theoretical. On the other hand, be wary of the implicit assumption. What is being described? This is C-style syntax that implies sizes are being considered in units of char. The above considers things at the word level. If the word length is not 2^n I would say all bets are off. -- Andrew Smallshaw andrews@sdf.org